1. Field of the Invention
The present invention relates to electronics, and more particularly to power supply systems.
2. Description of Related Art
Digital electronic devices often require a number of direct current voltage (DC Voltage) for proper operation. However, the devices usually receive power from a single or limited number of power sources (e.g., a power outlet or battery) which do not necessarily correspond to the required DC voltages.
Accordingly, a converter circuit is placed between the electronic device and the power source which receives an input DC voltage and produces a selectable DC voltage output. One type of converter is known as a switch mode power supply. Switch mode power supplies are characterized by the use of a high frequency switch with a varying duty cycle to maintain the output voltage.
A popular type of switch mode power supply is known as a Push-Pull converter. Referring now to FIG. 1, there is illustrated a diagram of Push-Pull converter, designated generally by the reference numeral 100. The Push Pull converter 100 includes an input node VIN for receiving an input voltage and an output node VOUT for supplying a steady selectable DC voltage to an electronic device, generally referred to as a load.
The Push-Pull converter 100 includes a primary circuit, designated generally by the reference numeral 100a, and an output section, generally designed by the reference numeral 100b, magnetically coupled together by a transformer T1. Transformer T1 includes primary windings T1a, and secondary windings T1b, in which a current passing through the primary windings T1a induces a proportional current through the secondary windings T1b, as is well understood to one skilled in the art.
The primary circuit 100 includes switches Q1 and Q2 which can include, for example, a transistor. The switches Q1, Q2 have respective gates G1 and G2, sources S1 and S2, and drains DR1 and DR2, in which the source and drain operate are short-circuited when a voltage exceeding the threshold voltage is applied across the gate and drain, and an open-circuit otherwise.
The output section 100b includes respective diodes D1 and D2, which permit current flow in one direction, but block current flow in the opposite direction. The diodes D1, D2 are schematically represented by an arrow which points in the direction in which current is permitted to flow. The condition where the diodes D1, D2 permit current flow is known as forward biasing, while the condition where diodes block current flow is known as reverse biasing. The output section 100b also includes an inductor L1 and an output capacitor C2 in what is known in the art as an LC filter network.
A voltage is applied across the gate G1, G2 and drain terminals DR1, DR2 by a gate drive circuit GDC, as illustrated in FIG. 1. The gate drive circuit GDC applies a square wave with less than 50% duty cycle to each switch Q1, Q2, where the square wave applied to Q2 is 180 degrees out of phase with the square wave applied across Q1.
When switch Q1 switches on, current flows through the upper half of transformer T1's primary winding T1a and the magnetic field in the transformer T1 expands. As is known in the art, the expanding magnetic field in the transformer T1 induces a voltage across the T1 secondary winding T1b. The polarity is such that diode D2 is forward biased and diode D1 reverse biased. Diode D2 conducts and charges the output capacitor C2 via L1. When switch Q1 turns off, the magnetic field in the transformer T1 collapses, and after a period of dead time, switch Q2 conducts, and current flows through the lower half of the primary winding T1a and the magnetic field in the transformer T1 expands. Now, however, the direction of the magnetic flux is opposite to that produced when switch Q1 conducted. The expanding magnetic field induces a voltage across the secondary winding T1b, the polarity of which is such that diode D1 is forward biased and diode D2 reverse biased. Diode D1 then conducts and charges the output capacitor C2 via L1. After a period of dead time, switch Q1 conducts and the cycle repeats.
As understood by those skilled in the art, the aforedescribed push pull converter 100 is well suited for medium to high power purposes. However, the push pull converter 100 also has a number of disadvantages. For example, the voltages across switches Q1 and Q2 are not tied to VIN, i.e., the input voltage, resulting in increased voltage stress across the respective switch. Furthermore, push pull converters 100 experience parasitic oscillations in the primary circuit 100a during the dead time due to the interaction of the capacitance of the switches Q1, Q2 and leakage inductance.
Accordingly, it is an object of the present invention to limit the voltage stress across the switches in the primary circuit.
It is also an object of the present invention to reduce the parasitic oscillations in the primary circuit.